A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO

Title
A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO
Authors
강진구
Keywords
Clock and data recovery, voltage controlled oscillator, half-rate linear phase detector, DisplayPort1.2, display interface
Issue Date
2013
Publisher
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
Series/Report no.
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE ; Vol13 no.3 Startpage 185 Endpage 192
Abstract
In this paper, a clock and data recovery (CDR) circuit that supports triple data rates of 1.62, 2.7, and 5.4 Gbps for DisplayPort 1.2 standard is described. The proposed CDR circuit covers three different operating frequencies with a single VCO switching the operating frequency by the 3-bit digital code. The prototype chip has been designed and verified using a 65 nm CMOS technology. The recovered-clock jitter with the data rates of 1.62/2.7/5.4 Gbps at 2 31 -1 PRBS is measured to 7/5.6/4.7 psrms , respectively, while consuming 11 mW from a 1.2 V supply.
URI
http://dx.doi.org/10.5573/JSTS.2013.13.3.185
http://dspace.inha.ac.kr/handle/10505/34297
ISSN
1598-1657
Appears in Collections:
College of Engineering(공과대학) > Electronic Engineering (전자공학) > Local Access Journals, Paper, Reports (전자공학 논문, 보고서)

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