Design of a 6-bit 500MS/s CMOS A/D Converter with Comparator-based Input Voltage Range Detection Circuit

Title
Design of a 6-bit 500MS/s CMOS A/D Converter with Comparator-based Input Voltage Range Detection Circuit
Authors
윤광섭
Keywords
Analog-to-digital converter, flash, range detection circuit
Issue Date
2013
Publisher
한국통신학회논문지
Series/Report no.
한국통신학회논문지; 제38권 제4호 pp 303~309
Abstract
A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13- um CMOS process.
URI
http://dx.doi.org/10.5573/JSTS.2014.14.6.706
http://dspace.inha.ac.kr/handle/10505/34290
ISSN
1226-4717
Appears in Collections:
College of Engineering(공과대학) > Electronic Engineering (전자공학) > Local Access Journals, Paper, Reports (전자공학 논문, 보고서)

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

Browse