A Study on the Design of Flash Analog to Quaternary Converter Using DLC Comparator

Title
A Study on the Design of Flash Analog to Quaternary Converter Using DLC Comparator
Authors
김흥수
Keywords
Flash Analog, Quaternary Converter, DLC Comparator
Issue Date
2003
Publisher
IEEE
Series/Report no.
Proceedings of The International Symposium on Multiple-Valued Logic ;
Abstract
This paper describes a 3.3V low power 4 digit CMOS flash analog to quaternary converter (AQC) designed with neuron MOS down literal circuit comparators and binary to quaternary encoding blocks. The neuron MOS down literal comparator allows the designed AQC to reduce not only the number of MOS transistors, but also power dissipations compared with conventional ADCs. Fast settling time and low power consumption of the AQC are achieved by utilizing the proposed architecture. The simulation results of the designed 4 digit AQC show a sampling rate of 16MHz and a power dissipation of 28.5mW with a single power supply of 3.3Vfor a double poly four metal standard CMOS 0.35 ? n-well technology.
URI
http://dspace.inha.ac.kr/handle/10505/29399
ISSN
0195-623X
Appears in Collections:
College of Engineering(공과대학) > Electrical Engineering (전기공학) > Local Access Journal, Report (전기공학 논문, 보고서)

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