광대역 통신시스템을 위한 순방향 오류정정 부호의 고성능 VLSI 구조 연구

Title
광대역 통신시스템을 위한 순방향 오류정정 부호의 고성능 VLSI 구조 연구
Authors
최창석
Keywords
광대역통신시스템을위한순방향오류정정부호의고성능vlsi구조연구
Issue Date
2012
Publisher
인하대학교
Abstract
In the modern broadband communication network, due to the growth of internet traffic together with an increase in a bandwidth and range of new services, both wire and wireless communication systems are rapidly evolving to support high transmission data rate. Especially, fiber-optic communication systems as a back-bone communication network, are now developing the 100-Gb/s transmission system. And the optical transport systems are further expected to reach up to 1-Tb/s within a decade. Wireless high-speed nearby communication represented by wireless personal area network (WPAN) technology, are also developing to support high data rate applications such as video on demand (VoD), high-definition television (HDTV) and 3D-videos. In this trend, high performance forward error correction (FEC) architecture which is essential in communication systems are required to support high-throughput and low-power consumption. In this thesis, I present efficient FEC architectures for various communicatio
Description
1 Introduction 1 1.1 Motivation of the Research 1 1.2 Objective of the Research 4 1.2.1 FECs for Broadband Communications 4 1.2.2 High-Throughput NB-LDPC Decoder Architecture 5 1.3 Outline of the Thesis 7 2 FEC Architectures for WPAN Systems 8 2.1 RS Codes for WPAN systems 9 2.1.1 Shortened RS Codes 10 2.2 Parallel RS Encoding 11 2.2.1 Three-Parallel RS encoding 11 2.2.2 Four-Parallel RS encoding 13 2.3 Parallel RS decoding 15 2.4 Syndrome Computation 16 2.4.1 Three-Parallel Syndrome Computation 16 2.4.2 Four-Parallel Syndrome Computation 19 2.5 Chien search and Error Correction 20 2.5.1 Three-Parallel Chien search and Error Correction 20 2.5.2 Four-Parallel Chien search and Error Correction 22 2.6 KES Architecture 26 2.7 Timing Chart 31 2.7.1 Timing Chart of Three-Parallel RS Enc/Dec 31 2.7.2 Timing Chart of Four-Parallel RS Enc/Dec 31 2.8 Simulation and Comparison 35 2.8.1 BER Performance Analysis 35 2.8.2 Implementation Results and Compariso
URI
http://dspace.inha.ac.kr/handle/10505/23518
Appears in Collections:
College of Engineering(공과대학) > Information and Communication Engineering (정보통신공학) > Theses(정보통신공학 석박사 학위논문)
Files in This Item:
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