Tuned Weight-Based Lottery Bus Algorithm for SoC

Title
Tuned Weight-Based Lottery Bus Algorithm for SoC
Authors
유봉
Keywords
tunedweightbasedlotterybusalgorithmforsoc
Issue Date
2011
Publisher
인하대학교
Abstract
On-chip communication architecture plays an important role in determining the overall performance of the system-on-chip design. SoC has several masters, slaves, arbiter and decoder in bus architecture. Master initiates the data transactions like CPU, DMA and DSP and slave responses the data transactions like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an important role in arbitrating a bus use. In compliance with the selection of arbitration method, SoC performance can be changed definitely. Fixed priority, round-robin, TDMA and Lottery policies are used in general arbitration method. On a SoC bus contentions occur while different IP cores request the bus access at the same time. Hence an arbiter is mandatory to deal with the contention issue on a shared bus system. In this thesis, A Tune Weight-based Lottery Algorithm and Bandwidth-aware Bus Arbitration Method are proposed to adjust the bandwidth As each master has previously defined priority in fixed priority method, the master having higher priority has high data transaction. But then, because the master having lowest priority always loses in the bus use competition with the other masters, it falls in starvation phenomenon that master cannot get the right of bus use for long time. Round-robin method is that the right of bus use is given to each master impartially. So, though it is possible to avoid the starvation phenomenon, higher priority is hardly assigned to the master that needs to transfer data urgently. TDMA and Lottery provide each master with slot number or ticket probability to assign the right of bus use with master priority and can prevent starvation phenomenon. In this thesis, A Tune Weight-based Lottery Algorithm using calculating the value of waiting time to prevent the starvation. The results show that the performance is improved when a different master's request pattern is changed dynamically due to different programs running on sy
Description
Contents List of Figures iii List of Lables v Abstract vi Chapter 1. Introduction 1 1.1 The background of SoC 1 1.2 SoC Communication Architectures 4 Chapter 2. Bus architecture model 5 2.1 AMBA AHB bus architecture 5 2.2 Overview of AMBA AHB operation 6 2.3 Basic transfer 8 2.4 Transfer type 9 Chapter 3. Typical arbitration mode 10 3.1 Fixed priority method 10 3.2 TDMA method 12 3.3 Round-robin method 14 3.4 Lottery bus method 17 Chapter 4. Proposed arbitration mode 19 4.1 Observations on Lottery arbitration algorithm 19 4.2 Tune Weight-Based Lottery Algorithm for SoC bus 20 4.2.1 Porposed arbitration architecture 20 4.2.1 Ticket generator 21 4.2.3 Model for performance analysis 24 4.2.4 Simulation results 26 4.3 Bandwidth-Aware Bus Arbitration Method 28 4.3.1 Concept of bandwidth-aware bus arbitration 28 4.3.2 Performance analysis 32 Chapter 5. Conclusion 39 Reference 40
URI
http://dspace.inha.ac.kr/handle/10505/22660
Appears in Collections:
College of Engineering(공과대학) > Electronic Engineering (전자공학) > Theses(전자공학 석박사 학위논문)
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